The present invention relates generally to power modeling for microprocessors and relates more specifically to contributor-based power modeling.
Power consumption is a key factor in the design of electronic products, since it directly affects thermal margins, cost, and reliability. At the same time, increasing process variation in the nanometer era complicates both power analysis and optimization. Power-aware design flows have been developed to address the challenges arising from increased design complexity and the need to control power consumption.
The increase in design complexity, and the need for accurate models, has necessitated complex power-aware design flows. The challenges in delivering accurate models are due at least in part to variations at the device level and variations at the block/function level. Variation occurs at the device level as a result of increases in process corners and of an exponential dependence of leakage on temperature and voltage. Variation at the block/function level occurs as a result of power saving features (e.g., clock gating, power gating) and widely varying workload characteristics).
For instance, a typical cell library includes hundreds of cells, each having multiple states and transistors. Cell library characterization usually generates power data for several process corners. However, when power analysis is being performed at the block level, library characterization may not be available at a requested process corner. In this case, one must interpolate between process corners for which library characterization data is available. This interpolation increases the run time of and may decrease the accuracy of the power analysis.
The above challenges are magnified when attempting to analyze a chip that comprises multiple blocks, particularly when the analysis must be performed under several different corner conditions and with several different workloads. Conventional power-aware design flows based on PVT (process, voltage, and temperature)-specific power models are not able to efficiently perform the necessary hierarchical analysis at the chip level.